1. Field of the Invention
This invention relates to a circuit arrangement for monitoring the function of a decoder circuit which comprises at least parallel connected decoder transistors, a pre-charging transistor and an end stage which samples the output signal of the decoder transistors, and more particularly to such an arrangement in which the decoder circuit is simulated through the utilization of two discharge transistors which are connected in parallel and have control inputs which are supplied with address signals in inverted form and in non-inverted form and a node which is formed by the one connection point which is pre-charged in that it is connected to a further transistor.
2. Description of the Prior Art
For the operation of integrated storage modules which, for example, are constructed in the dynamic MOS technique, it is necessary, immediately after decoding of the addresses, to produce an internal clock pulse which activates the selected rows and column of the storage section. If this selection clock pulse is triggered before the expiration of the decoder time, a multiple selection, and thus a mis-selection, occurs. If a clock pulse is produced too late, the storage module operates reliably, but unnecessary time losses occur in the clock pulse flow. It must be taken into consideration that the straying of the technological and electrical parameters means that the decoder time is subject to specific fluctuations so that it is not possible to utilize a rigid time selection clock pulse in order to achieve a reliable and high speed operation of the storage module.
In order to produce the selection clock pulse as far as possible at the correct time, it is known in the art to provide a monitoring circuit for the decoder circuit in which the address signals are decoded. A known monitoring circuit is illustrated in FIG. 2 and is to be described in association with a known decoder circuit corresponding to that illustrated in FIG. 1.
The decoder circuit illustrated in FIG. 1 comprises parallel-arranged decoder transistors M2, M3 and M4 which are operated by address signals A1, A2 and A3. The common connection point K of the decoder transistors M2, M3 and M4 is also connected to a pre-charging transistor M1 which is operated by a pre-charging clock pulse .phi.V and on the other hand is connected to an operating voltage UDD. The connection point, which in the following will be referred to as a node K, is also connected to an end stage which consists of an inverter stage comprising the two transistors M5 and M6, and a coupling capacitor C2. The control input of the inverter transistor M5 is connected to a terminal of the controlled path via the coupling capacitor C2. The node K is connected to a capacitance C1 which is illustrated in broken lines. The latter is formed by the diffusion capacitance of the decoder transistors M2, M3 and M4, by the coupling capacitance C2 and the input capacitance of the inverter transistor M5. The transistor M5 is also connected to the selection clock pulse .phi.A. The operation of such a decoder circuit is well known in the art and therefore does not require a detailed explanation thereof.
The operation of the decoder circuit can be monitored with the aid of the monitoring circuit illustrated in FIG. 2. The monitoring circuit comprises two parallel-connected transistors M12 and M13 which are supplied with an address signal in non-inverted form and in inverted form. The address signal can, for example, be the address signal A1 and A1. A transisotr M10 is also provided which is likewise operated by a pre-charging clock pulse .phi.V and which is connected to the connection point K1 of the two transistors M12 and M13 and is also connected to the operating voltage UDD. The connection point -- the node K1 -- is connected to a capacitance C10 which is formed by the diffusion capacitance of the transistors M12 and M13 and the capacitance of the end stage (not shown).
The monitoring circuit illustrated in FIG. 2 operates as follows. The capacitance C10 connected to the node K1 of the circuit is pre-charged via the transistor M10 with the pre-charging clock pulse .phi.V. During this pre-charging phase, the true and inverted address signals are clamped to the potential of 0V. Therefore, the transistors M12 and M13 are blocked. At the beginning of the read-out or write-in process, either the true or the inverted address signals A1, or A1, rises to a high potential. Therefore, the capacitance C10 is discharged via one of the transistors M12 and M13. The discharge time is dependent upon the capacitance C10 and the discharge current which flows through transistors M12 aND M13. Here, the discharge current is also fundamentally codetermined by the ratio of the width to the length of the channel of the transistor M12, M13 which discharges the capacitance C10. If the monitoring circuit which simulates the decoder circuit is constructed in accordance with the decoder circuit, the discharge time of the monitoring circuit corresponds to the discharge time of the decoder circuit. Therefore, if the node K1 is sampled by an end stage, the latter emits an output signal when the node K1 is discharged. However, this is also an indication that the decoder circuit has decoded the address signals.
In order, however, to construct the monitoring circuit in accordance with the decoder circuit, it is necessary for the monitoring circuit to be designed in respect of its capacitive load to be identical with the decoder circuit, and that the transistors M12 and M13 should be dimensioned in accordance with the decoder transistors. If, however, for reasons of space, the capacitance C10 of the monitoring circuit is selected to be smaller than the capacitance C1 in the decoder circuit, the transistors M12 and M13 must also be reduced in size to the same extent. The fluctuations in the discharge current, which then increase, lead, however, to increasing fluctuations in the discharge time so that simulation of the decoder circuit becomes increasingly unreliable. Here, it must also be taken into account that the monitoring circuit comprises only two transistors M12 and M13, whereas the decoder circuit contains a larger number of decoder transistors.
The known monitoring circuit illustrated in FIG. 2 is utilized not only for the decoder circuit corresponding to FIG. 1, but also for decoder circuits of more complicated construction. In decoder circuits with such complicated construction, further circuit elements are arranged between the node K and the end stage. These further circuit elements then also influence the capacitive loading of the node K. In addition, it is then no longer the potential of the node K which is sampled by the end stage, but the potential present at the input of the one inverter transistor of the end stage. This potential at the input of the inverter stage lags behind, in time, the potential connected to the node K.